1. Field of the Invention
The present invention relates to a reproducing apparatus and, more particularly, to an apparatus for reproducing a clock signal from a digital signal reproduced from a recording medium.
2. Description of the Related Art
It has heretofore been known that a phase-locked loop (hereinafter referred to as "PLL") is used to extract a clock signal phase-synchronized with a reproduced signal, from a received data train in an apparatus, such as a digital VTR, which transmits (records and reproduces) data at high speed.
A circuit of the type shown in FIG. 1 is used as a circuit for generating such a clock signal from a digital signal reproduced from a recording medium.
Referring to FIG. 1, a digital signal reproduced from a recording medium (not shown) is amplified by an amplifier and equalized by an equalizer (not shown), and the reproduced digital signal outputted from the equalizer is applied to one input of a phase comparing circuit 102 via an input terminal 101.
The output of a voltage controlled oscillator (VCO) 119 which will be described later is applied to the other input of the phase comparing circuit 102.
The phase comparing circuit 102 generates a signal having a voltage proportional to the phase difference between the two input signals, and outputs the signal to a loop filter 103. The loop filter 103 is made up of resistances 104 and 106, an amplifier 105, a capacitor 107 and diodes 108 and 109 which function to limit their respective output voltages within .+-.0.7 V. The loop filter 103 suppresses the high-frequency component of the input signal and applies the resultant signal to one input of an adder 110. A switch 301 is connected across the input and output terminals of the amplifier 105.
In the meantime, a reference signal having a frequency approximately equal to the center frequency of a clock signal extracted from the reproduced digital signal which contains jitter is applied to the input terminal 302 from an oscillator (not shown), and the reference signal is applied to one input of a frequency/phase comparing circuit (hereinafter referred to as "FPC") 303. The output of the VCO 119 is applied to the other input of the FPC 303. The FPC 303 compares the frequency and phase of the reference signal with those of the output of the VCO 119, respectively, and outputs the comparison result to a switch 304. Incidentally, the FPC 303 may be, for example, Motorola's MC12040.
The switch 304 is closed at a timing which will be described later, and when the switch 304 is closed, the output of the FPC 303 is applied to a loop filter 305. The loop filter 305 is made up of an amplifier 309, resistances 306 and 307 and a capacitor 308, and the output signal of the loop filter 305 is applied to the other input of the adder 110.
The adder 110 adds together the voltages of the two input signals, and outputs the sum to the VCO 119.
The circuit shown in FIG. 1 has a state (mode A) in which the phase is made coincident with that of the reproduced signal applied to the input terminal 101 and a state (mode B) in which the frequency and the phase are made coincident with those of the reference signal applied to the input terminal 302. If the switches 301 and 304 are open, the circuit selects the mode A, whereas if they are closed, the circuit selects the mode B.
When the circuit is in the mode A, a phase-locked loop (hereinafter referred to as "PLL") is formed. In the PLL, a phase error between the output signal of the VCO 119 and the reproduced signal applied to the input terminal 101 is inputted to the loop filter 103, and the loop filter 103 averages the input phase error and outputs to the VCO 119 a signal having a voltage capable of cancelling the phase error between the output signal of the VCO 119 and the reproduced signal. During the mode A, since the switch 304 is open, the output of the amplifier 309 is maintained at a constant voltage.
When the circuit is in the mode B, a feedback loop is formed. In the feedback loop, the FPC 303 compares the reference signal inputted through the input terminal 302 with the output signal of the VCO 119 and inputs a signal indicative of the obtained error to the loop filter 305. The loop filter 305 averages the output signal of the FPC 303 and outputs to the VCO 119 through adder 110 a signal having a voltage capable of reducing the error. During the mode B, since the switch 301 is closed, the output of the amplifier 105 is held at zero.
FIG. 2 shows the timing of switching between the mode A and the mode B. The waveform shown in FIG. 2 is an example of a reproduced envelope. During the time period in which an envelope is present, the mode A is selected and the PLL is operated by employing the reproduced signal, thereby producing a clock signal. During the time period in which no envelope is present, since phase lock based on the reproduced signal is impossible, the mode B is selected and the oscillation frequency of the VCO 119 is made approximately coincident with a frequency to which the PLL is to be locked when the next envelope is obtained.
According to such an arrangement, even if the oscillation frequency of the VCO 119 varies with a temperature variation or the like, the mode B is selected so that the frequency of the VCO 119 can be held approximately in the center of the lock range of the PLL at all times.
However, the above-described conventional example requires a multiplicity of analog constituent components such as an FPC and an oscillator for generating a reference signal. This leads to a number of problems such as an increase in the size of the whole circuit, an increase in the price of the apparatus, and the inferior reliability of the analog circuit.
In addition, the conventional example, which is incapable of reproducing data during the mode B, cannot be applied to a case in which continuous data is needed.